Lucrarea 3 VHDL - Semnale. Parametri generici. Constante (18 martie)

Memorie ROM (ieşirea pe un bit)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
    port (A:in std_logic_vector(3 downto 0);
    C:out std_logic);
end rom;

architecture Arch of rom is
signal Harta:std_logic_vector (15 downto 0):="0110100110101010";
begin
    C<=Harta(CONV_INTEGER(A));
end Arch;

Xilinx

NET "A(3)" LOC=T5;
NET "A(2)" LOC=V8;
NET "A(1)" LOC=U8;
NET "A(0)" LOC=N8;
NET "C" LOC=U16;

Memorie ROM (ieşirea pe doi biţi)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rom is
    port (A:in std_logic_vector(3 downto 0);
    C:out std_logic_vector(1 downto 0));
end rom;

architecture Arch of rom is
type MM is array(15 downto 0) of std_logic_vector (1 downto 0);
signal Harta:MM:=("00","01","11","10","11","11","11","00","01","10","01","11","10","11","11","11");
begin
    C<=Harta(CONV_INTEGER(A));
end Arch;

Memorie RAM (ieşirea pe doi biţi)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity RAM is
    port (WE:in std_logic;
    A:in std_logic_vector (3 downto 0);
    DIN:in std_logic_vector (1 downto 0);
    C:out std_logic_vector (1 downto 0));
end RAM;

architecture Arch of RAM is
type MM is array (15 downto 0) of std_logic_vector(1 downto 0);
signal Harta:MM:=("00","01","10","11","00","01","10","11","00","01","10","11","00","01","10","11");
begin
    process
    begin
        if (WE='0') then
            C<=Harta(CONV_INTEGER(A));
        end if;
        if(WE='1') then
            Harta(CONV_INTEGER(A))<=DIN;
        end if;
    wait on WE,A,DIN;
    end process;
end Arch;