Lucrările 6 şi 7 VHDL - Domeniul secvenţial. Procese (6), Instrucţiuni secvenţiale (7) (8 aprilie)

Numărător - Active HDL

library    IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all; 

entity ent_numarator is
    Port (CLK: in STD_LOGIC;
    R:in STD_LOGIC;
    L:in std_logic;   
    INPUT: std_logic_vector (3 downto 0);
    Q:out STD_LOGIC_VECTOR (3 downto 0)); 
end ent_numarator;

architecture arh_numarator of ent_numarator is
begin
process(CLK)      
variable intQ:std_logic_vector(3 downto 0);
    begin
        if (clk'event and R='1') then
            intQ:="0000";
        elsif (clk'event and clk='1') then   
            if(intQ="1111") then
                intQ:="0000";
            else
                intQ:=intQ+'1';
            end if;
        elsif (clk'event and L='1') then
            intQ:=INPUT;
        end if;     
    Q<=intQ;
end process;
end arh_numarator;             

Numărător - Xilinx

library    IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all; 

entity ent_numarator is
    Port (CLK: in STD_LOGIC;
    R:in STD_LOGIC;
    L:in std_logic;   
    INPUT: std_logic_vector (3 downto 0);
    Q:out STD_LOGIC_VECTOR (3 downto 0)); 
end ent_numarator;

architecture arh_numarator of ent_numarator is
begin
process(CLK)      
variable intQ:std_logic_vector(3 downto 0);
    begin
        if (clk='1' and clk'event) then
            if(r='1') then
                intQ:="0000";
            elsif (l='1') then
            intQ:=INPUT;
            else intQ:=intQ+'1';
            end if;
        end if;
       
    Q<=intQ;
end process;
end arh_numarator;

NET "D(3)" LOC = T5;
NET "D(2)" LOC = V8;
NET "D(1)" LOC = U8;
NET "D(0)" LOC = N8;
NET "Reset" LOC = T9;
NET "Load" LOC = T10;
NET "Q(3)" LOC = T11;
NET "Q(2)" LOC = R11;
NET "Q(1)" LOC = N11;
NET "Q(0)" LOC = M11;
NET "CLK" LOC = B8;

Divizor de frecvenţă - nefuncţional (un led se aprinde o dată pe secundă)

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;   

entity numarator is
    port (CLK:in STD_LOGIC;
    CLK1:out STD_LOGIC);
end;

architecture arh1 of numarator is
begin
process(CLK)
    variable K:STD_LOGIC:='0';
    variable X:INTEGER RANGE 0 to 100_000_000;
    begin
        --if (CLK'EVENT and CLK='1') then
        --    X:=X+1;
        --end if;
       
        --if (X=99_999_999) then
        --    K:='1';
        --    X:=0;
        --else K:='0';
        --      X:=X+1;
        --end if;
       
       
        CLK1<=CLK;
    end process;
end arh1;

Reclamă luminoasă - inexistent